High performance galvanic switches enable multiplexing of electric signals without buffering. Galvanic multiplexers are inherently bidirectional and conceptually simple. These properties create many opportunities for extending the number of ports by increasing the number of switches so long as the switch characteristics do not significantly affect the integrity of the signals.
A simple example of a configuration of a multiplexer is a circuit that selectively connects an input port to a specific one of multiple output ports. The input port is connected to each respective one of the output ports via a respective one of multiple switch elements. In MOS-technology (metal-oxide-silicon technology), a switch element is typically implemented with a pass-gate. The control terminals of the pass-gates are driven to supply levels such that a specific one of the pass-gates has low-impedance (pass transistors turned on) and the other pass-gates have high-impedance (pass transistors turned off). Disadvantages of this solution are the dependence of the on-resistance on the supply voltage and on the level of the signal voltage, and the capacitive loading caused by these switch elements on the signal lines.
For multiplexing of high-speed communication signals that are transported via transmission lines, it is preferred that the selected path through the multiplexer causes no, or hardly any, insertion losses and reflection losses. This requires a low parasitic loading capacitance to the signal lines in order to limit discontinuity at high frequencies. Furthermore, the series resistance must be low compared to the characteristic impedance, in order to reduce all-frequency signal attenuation and reflections. The lower the on-resistance and the lower the capacitance, the less impact a multiplexer will have on the signal integrity and the higher will the signal speeds be for which the multiplexer can be used. Lower impact on signal integrity also allows for more multiplexing paths in the multiplexer and/or for multiple cascaded multiplexers. Therefore, it is very interesting to have high-performance switching elements with low on-resistance and low load-capacitance.
In CMOS technologies with multiple gate-oxide thicknesses, it is preferable to use the devices which provide the best bandwidth and best on-resistance versus load capacitance trade-off. This will usually be the thinnest oxide transistors with smallest gate-length but, unfortunately, these devices cannot withstand large voltages across their terminals.
Furthermore, low on-resistance and low capacitance are conflicting requirements as the former implies a larger transistor width and the latter implies a smaller transistor width.
Complementary pass-gates are not very effective, as PMOS devices are weaker than NMOS devices of the same size and using the same bias and, therefore, need to have a larger width and/or more bias to obtain similar on-resistance. Accordingly, unless the PMOS device can have substantially more bias than the NMOS device, increasing the size of a PMOS device increases the load capacitance more than it helps to reduce overall on-resistance and, therefore, penalizes performance.
As an alternative to a pass-gate implemented with both NMOS devices and PMOS devices, an NMOS-only pass-gate can be used. However, for higher signal-levels, the impedance of the NMOS device will increase.
Consider, for example, an MOS-technology with thin-oxide devices for a 1.8V supply voltage and thicker-oxide devices suitable for a 4V supply voltage. A thin-oxide NMOS device, having its gate connected to the 1.8V supply voltage, will not be suitable to pass signal levels with low series-impedance between 0V and 1.8V, due to an insufficient gate drive. Increasing the gate voltage would stress the transistors in case of low signal-voltages and, therefore, compromise life-time and robustness.
Instead, a thick-oxide NMOS device can be applied with a high gate-drive voltage of, for example, 4V. This provides sufficient voltage to keep the transistor of the selected path turned on. However, the on-resistance will vary substantially with the signal level and the thick-oxide device causes substantially higher capacitive loading of the signal lines for the same on-resistance.